Stacked SiGe nanosheets p-FET for Sub-3 nm logic applications

The fabrication of vertically stacked SiGe nanosheet (NS) field-effect transistors (FETs) was demonstrated in this study. The key process technologies involved in this device fabrication are low pressure chemical vapor deposition SiGe/Si multilayer epitaxy, selective etching of Si layers over SiGe layers using tetramethyl-ammonium-hydroxide wet solution, and atomic layer deposition of Y2O3 gate dielectric. For the fabricated stacked SiGe NS p-GAAFETs with a gate length of 90 nm, ION/IOFF ratio of around 5.0 × 105 and subthreshold swing of 75 mV/dec were confirmed via electrical measurements. Moreover, owing to its high quality of Y2O3 gate dielectric, the device showed a very small drain-induced barrier-lowering phenomenon. These designs can improve the gate controllability of channel and device characteristics.

In response to market demands, CMOS technologies continuously aim to scale down the device dimension as much as possible. Nevertheless, miniature Si metal-oxide-semiconductor field-effect transistors (MOSFETs) have encountered many fundamental physical limits; the accompanying difficulties in either developing required process technology or enhancing device performance are also increased. Simply shrinking the channel length and/or the dielectric thickness can no longer realize the excellent switching ratio, high driving capability, low leakage current, and acceptable reliability. Compared to pure Ge channel FET, SiGe channel FETs will be most likely utilized beyond 3-nm technology node because of the absence of dislocations resulting from the smaller lattice mismatch with Si 1 . Thus, rapid development in SiGe technologies is warranted, and relevant studies in this field are needed [2][3][4][5][6][7][8][9][10][11][12][13] .
Many reports regarding the stacked channel FETs have been published. However, few studies have reported on the stacked SiGe channel FETs. The main reason behind this is that selective etching of Si over SiGe is a difficult process. In this work, we fabricated vertically stacked SiGe nanosheet (NS) FET devices on cost-effective traditional Si substrates by selective etching of Si in SiGe/Si/SiGe stack structures using wet tetramethyl-ammonium-hydroxide (TMAH) solution to form stacked SiGe NS channels. The fabrication process exhibits various advantages. (1) isotropic etching without ion bombardment with extremely high Si to SiGe selective etching rate ratio; (2) better control of the composition, thickness, and spacing of SiGe channel materials; (3) low process complexity, which is in line with standard process and mass production. These advanced designs can improve the gate controllability of channel and device characteristics. As the semiconductor-related field gradually enters its physical limitations, Si/SiGe/Si/SiGe epitaxial multi-layer combined with selective etching is considered as the most likely implementation of the vertically stacked SiGe 14,15 .
In this work, selective etching of Si over SiGe was systematically studied and a complete process-flow for the formation of vertically stacked SiGe channels was developed. Recently, highly selective etchants were demonstrated in our group 1 , which enabled the fabrication of SiGe NS using a wet-etching approach. After selective etching, optimization was done to achieve high-k gate oxide solutions on p-FET channels and obtain an applicable interface quality for demonstration.

Device fabrication
The fabrication procedure of two stacked p-type SiGe NS gate-all-around field-effect transistor (p-GAA FETs) is illustrated in Fig. 1. Two periods of Si 0.8 Ge 0.2 (60 nm)/Si (25 nm) layers were epitaxially grown on 200 mm SOI (100) substrate with a top Si thickness of 40 nm and a buried oxide thickness of 150 nm by low pressure chemical vapor deposition (LPCVD) using Dichlorosilane and GeH 4 gases. The GeH 4 and DCS flow rates were set to 25 and 130 sccm, respectively. When only Si layer was grown, the GeH 4 was switched to vent mode (that is, GeH 4 bypassed the chamber). The growth temperature and pressure were kept at 700 °C and 20 torr for all layers. A specific SiGe/Si epitaxy was employed to stack NS channels, with Si being used as a sacrificial layer that defines www.nature.com/scientificreports/ the suspension thickness between the channels. Figure 2 shows the transmission electron microscopy (TEM) cross-sectional images of the SiGe/Si multilayer epitaxy. The alternative layer thickness was well-controlled giving precise film thickness. X-ray diffraction (XRD) rocking curve analysis and reciprocal space mapping (RSM) in Fig. 3 show that the SiGe layers in the stacking SiGe/Si multilayers are fully strained, implying that the SiGe layers are not relaxed, and therefore no dislocations are generated. This results can also be supported by TEM images in Fig. 2 Figure 4 shows the stacked Si 0.8 Ge 0.2 NS structures after selective etching. As shown in Fig. 4a, the stacked Si 0.8 Ge 0.2 NS with a nanosheet width (W NS ) of ~ 100 nm is released. The N 2 blow drying process on the sample after wet-etching must be performed cautiously. Strong N2 blowing would lead to the issue of NS bending (see Fig. 4b). The resultant NS thickness is greater than 30 nm, and it is possible to obtain a thinner NS and higher W NS with further optimization. Subsequently, the 3 nm high-k dielectric Y 2 O 3 gate dielectric was deposited by atomic layer deposition (ALD) and TiN gate metal layer was deposited by PVD sputtering with a thickness of 75 nm. The deposited thickness of TiN on the sidewall was ~ 60 nm. After gate patterning, the S/D regions were formed by ion-implanted using 11 B ions for SiGe nanosheets p-FET (1 × 10 15 cm −2 at 10 keV). Activation was accomplished by annealing at 900 ℃ for 30 s. A simplified process flow with selected cross-sectional SEM pictures from critical steps is shown in Fig. 5.

Results
In our previous work, we had reported SiGe MOS interfacial properties using a gate stack of Y 2 O 3 with ten cycles of TMA pre-treatment. The scalability of EOT via reduction in film thickness of Y 2 O 3 and its effects on the properties of Si 0.8 Ge 0.2 MOS interfaces still remained unclear 16,17 . In this work, the feasibility of EOT scaling in TiN/Y 2 O 3 gate stacks with TMA treatment was examined. Figure 6a shows   However, C-V characteristics indicated sufficient performance of this gate stack for further device fabrication. Finally, I D -V GS and I D -V DS curves for the nanosheets p-FETs are shown in Fig. 7a and b, respectively. In  Table 1 shows a comparison of Si 0.8 Ge 0.2 stacked NS GAAFETs in this study with other GAAFETs that use different stacked channels.  www.nature.com/scientificreports/ We found there would be a remaining Si parasitic channel underneath the Si 0.8 Ge 0.2 NS and the shape of SiGe nanosheet would distort if the process of selective wet etching of Si sacrificial layers is not optimized (see Fig. 8), for instance, the temperature of TMAH solution is lower than 60 °C and concentration is less than 2.38%. The electrical measurement in Fig. 8b shows this parasitic Si channel influences the overall device performance by showing worse SS characteristic. Besides, the irregular shape of Si 0.8 Ge 0.2 channel was observed to give relatively    www.nature.com/scientificreports/ less overall perimeter compared to the rectangle nanosheet structure. Consequently, this will reduce the I on current of the device.

Conclusion
This study demonstrates the stacked Si 0.8 Ge 0.2 NS p-FETs using Si/SiGe multilayers. Selective etching of Si over SiGe processes was successfully developed to obtain the Si 0.8 Ge 0.2 nanosheets. The stacked SiGe NS GAAFETs have the potential to fulfill the requirement for the 3 nm technology node and beyond. Future studies will focus on further optimization of its performance terms of etch-selectivity and I on current. The technique demonstrated in this study has a significant potential to boost the p-FET device performance for the next generation of CMOS logic in GAA NS technology.

Methods
Si-on-insulator (SOI) wafers with a 40 nm thick Si top layer (p-type, 9-18 Ω cm) were employed as the substrates. The wafers were cleaned using the RCA standard cleaning methods for removing organic materials, certain metals, and particles from the Si substrates; the wafers were subsequently rinsed in deionized water and dried in N 2 gas. Four alternative layer stacking of SiGe (60 nm) and Si (25 nm) were epitaxially grown on SOI (100) wafer with a 40 nm Si top seed layer. GeH 4 and DCS gases were used to build the layer using an ASM Epsilon 2000 + low-pressure CVD machine. The growth temperature for the SiGe and Si layer was 700 °C. The growth pressure in chamber was kept at 20 torr. Electron-beam lithography and dry etching with Cl 2 /HBr were utilized to define and form the active device area, respectively. TMAH solution at 60 °C was used to remove Si interlayers selectively and form the stacked SiGe nanosheets. The gate dielectrics Y 2 O 3 were formed by ALD 18 . The gate metal TiN was deposited by PVD sputtering.